The present disclosure relates to harmonic distortion correction circuits, and more specifically, to third-order harmonic distortion correction circuit using a reference analog to digital converter.
High resolution, high speed analog to digital converters (ADCs) may be used in 5G mobile base stations, among other uses. The signal to noise and distortion ratio (SNDR) of high resolution ADCs in systems managing greater than 10 effective number of bits (ENOB) at high sampling rates is often limited by harmonic distortion, because of incomplete settling or nonlinear buffer/amplifier. ADCs at low sampling frequency can make use of feedback to reduce distortion. However this approach may not work with multi-GS/s ADCs.